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PRELIMINARY
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO3.3V LVPECL FANOUT BUFFER
ICS8535BI-01
GENERAL DESCRIPTION
The ICS8535BI-01 is a low skew, high performance IC S 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout HiPerClockSTM buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS8535BI-01 has two single ended clock inputs. the single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8535BI-01 ideal for those applications demanding well defined performance and repeatability.
FEATURES
* Four differential 3.3V LVPECL outputs * Selectable CLK0 or CLK1 inputs for redundant and multiple frequency fanout applications * CLK0 or CLK1 can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 266MHz * Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels * Output skew: TBD * Part-to-part skew: TBD * Propagation delay: 1.3ns (typical) * Additive phase jitter, RMS: 0.04ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature
PIN ASSIGNMENT
nQ1 Q1 VCC nQ0 Q0 VEE CLK_EN CLK_SEL nc CLK0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q2 nQ2 VCC nc Q3 nQ3 VCC nc nc CLK1
* Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
CLK_EN D Q LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 VCC Q2 nQ2 VCC nc Q3 nQ3
ICS8535BI-01
20-Lead TSSOP 4.4mm x 6.5mm x 0.925mm body package G Package Top View
nQ0
NQ1
VCC nQ3 Q3 VEE CLK_EN
1 2 3 4 5
20 19 18 17 16 15 14 13 12 6
CLK_SEL
7
CLK0
8
nc
9
CLK1
11 10
nc
ICS8535BI-01
20-Lead VFQFN 4mm x 4mm x 0.925mm body package K Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT TM / ICSTM 3.3V LVPECL FANOUT BUFFER
VCC
Q0
Q1
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Name VEE CLK_EN CLK_SEL CLK0 CLK1 nc VCC nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 NOTE: Pullup Power Input Input Input Input Unused Power Type Description Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Pullup Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. Pulldown LVCMOS / LVTTL interface levels. Pulldown LVCMOS / LVTTL clock input. Pulldown LVCMOS / LVTTL clock input. No connect. Positive supply pins.
Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Output and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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PRELIMINARY
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs CLK_EN 0 0 1 CLK_SEL 0 1 0 Selected Source CLK0 CLK1 CLK0 Q0:Q3 Disabled; LOW Disabled; LOW Enabled Outputs nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
1 1 CLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 1. In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Disabled
Enabled
CLK0, CLK1
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current 4.6V -0.5V to VCC + 0.5V 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 20 Lead TSSOP 73.2C/W (0 lfpm) 20 Lead VFQFN 60.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 45 Maximum 3.465 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1 CLK_EN, CLK_SEL CLK0, CLK1, CLK_SEL CLK_EN CLK0, CLK1, CLK_SEL CLK_EN VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 1.3 0.8 150 5 Units V V V V A A A A
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
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PRELIMINARY
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t sk(o) t sk(pp) t jit t R / tF Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time = 155.52MHz (Integration Range: 12kHz - 20MHz) 20% to 80% @ 50MHz 1.3 TBD TBD 0.04 450 Test Conditions Minimum Typical Maximum 266 Units MHz ns ps ps ps ps
odc Output Duty Cycle 50 % All parameters measured at 266MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz
0 -10 -20 -30 -40 -50 -60
band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.04ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
PART 1 nQx Qx
LVPECL
nQx VEE
PART 2 nQy Qy tsk(pp)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
nQx 80% Qx nQy Qy
tsk(o)
80% VSW I N G
Clock Outputs
20% tR tF
20%
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nQ0:nQ3 CLK0, CLK1 nQ0:nQ3 Q0:Q3
tPD
Q0:Q3
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
PROPAGATION DELAY
OUTPUT DUTY CYCLE/ PULSE WIDTH/PERIOD
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PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CLK INPUTS For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 3. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535BI-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8535BI-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 45mA = 155.9mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power_MAX (3.465V, with all outputs switching) = 155.9mW + 120mW = 275.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.276W * 66.6C/W = 103.38C. This is well below the limit of 125C. This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA
FOR
20-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. JAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 60.4C/W
1
52.8C/W
3
46.0C/W
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PRELIMINARY
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 1.0V
*
For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V
L
CC_MAX
- VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V - (V - 2V))/R ] * (V
L
OL_MAX
CC_MAX
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 60.4C/W
1
52.8C/W
3
46.0C/W
TRANSISTOR COUNT
The transistor count for ICS8535BI-01 is: 412
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PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 6.40 Minimum
FOR TSSOP
Millimeters Maximum 20 1.20 0.15 1.05 0.30 0.20 6.60 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
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PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below.
TABLE 8B. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.75 0.35 0.75 4.0 2.80 0.75 0.18 0.50 BASIC 5 5 4.0 2.80 0.80 0 0.25 Reference 0.30 MINIMUM 20 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8535BGI-01 ICS8535BGI-01T ICS8535BGI-01LF ICS8535BGI-01LFT ICS8535BKI-01 ICS8535BKI-01T ICS8535BKI-01LF ICS8535BKI-01LFT Marking ICS8535BGI01 ICS8535BGI01 ICS8535BI01L ICS8535BI01L 35BI01 35BI01 5BI01L 5BI01L Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead Free" TSSOP 20 Lead "Lead Free" TSSOP 20 Lead VFQFN 20 Lead VFQFN 20 Lead "Lead-Free" VFQFN 20 Lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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www.IDT.com
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Corporate Headquarters
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Asia Pacific and Japan
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Europe
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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